B&B Electronics Asynchronous to Synchronous Converter 2010 Manual do Utilizador descarregar pdf (Página 11)

Department of Computer Science and Electronics

2.2.3. ADC

The ADC is connected to an 8-channel Analogue Multiplexer which allows 8

single-ended voltage inputs constructed from the pins of Port A. The single-ended

voltage inputs refer to 0V (GND).

The ADC converts an analogue input voltage to a 10-bit digital value through

successive approximation. The minimum value represents GND and the maximum

value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an

internal 2.56V reference voltage may be connected to the AREF pin by writing to the

REFSn bits in the ADMUX Register.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. It

generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted.

A single conversion is started by writing a logical one to the ADC Start

Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and

will be cleared by hardware when the conversion is completed. If a different data

channel is selected while a conversion is in progress, the ADC will finish the current

conversion before performing the channel change.

By default, the successive approximation circuitry requires an input clock

frequency between 50 kHz and 200 kHz to get maximum resolution. This must be set in

the ADCSRA register.

There exists more than one mode to do the conversion such as, auto triggered

mode, free running mode or single conversion. Latter is used and explained in the

following lines.

A normal conversion takes 13 ADC clock cycles. The first conversion after the

ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to

initialize the analog circuitry as shows the figure 2-7. In addition, in the figure 2-7 can

see that the actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a

normal conversion and 13.5 ADC clock cycles after the start of a first conversion. That

why it is recommendable to ignore the first conversion (figure 2-6).

When a conversion is complete, the result is written to the ADC Data Registers.

In single conversion mode, ADSC is cleared simultaneously. The software may then set

ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

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