B&B Electronics PC Watchdog Timer Card ATRWDT Manual do Utilizador descarregar pdf (Página 14)

P104-WDG-CSM User Manual

Chapter 4: Programming

This section of the manual contains information to assist you in developing programs for use

with the card. I/O bus address assignments, programming hints, and a description of the utility

driver are included.

The card uses sixteen consecutive registers in I/O space as listed in the following table:

Address Read Write

Base Address Counter #0 Real-time Value Counter #0 Load Value

Base Address +1 Counter #1 Real-time Value Counter #1 Load Value

Base Address +2 Counter #2 Real-time Value Counter #2 Load Value

Base Address +3 Unused Counter #0-2 Control Register

Base Address +4 Status Register, Clear IRQ, Enable IRQs IRQ Enable Register

Base Address +5 8-bit Temperature Value Unused

Base Address +6 0-5V Analog 1 8-bit Value Unused

Base Address +7 Disable Counters Enable Counters

Base Address +8 Status Register Image Unused

Base Address +9 Disable Interrupts Unused

Base Address +A 0-5V Analog 2 8-bit Value Unused

Base Address +B Light Sensor 8-bit Value Unused

Base Address +C Hi Rate Clock Select (16MHz) Low Rate Clock Select (2MHz)

Base Address +D

Isolated Output1 (and LED1) Off

(P1-2,29 High)

Isolated Output1 (and LED1) On

(P1-2,29 Low)

Base Address +E

Isolated Output2 (and LED2) Off

(P1-6,31 High)

Isolated Output2 (and LED2) On

(P1-6,31 Low)

Base Address +F Control Register Circuit Status Circuit Enable/Disable

Table 4-1: Register Address Map

Three events will generate an active-low RESET at P1-12:

1. 32 bit timer counts down to zero, must be enabled with CONTROL register bit 0 or with a

WRITE at base+7. READ base+7 to stop the counters or write 0 to CONTROL bit 0. The

RESET persists as long as the output of counter 2 is HIGH.

2. The active-low reset push button input at P1-16 when CONTROL register bit 5 is set.

3. Current driven thru the isolated input #2 circuit when CONTROL register bit 3 is set.

Seven events may generate interrupts

If interrupt enable register bit 7 is set or if base+4 is read or if CONTROL register bit 7 is set:

1. 32 bit timer counts down to zero and interrupt enable register bit 0 is set.

2. The temperature sense circuit detects ~122F and interrupt enable register bit 1 is set.

3. 5 volt overvoltage is detected and interrupt enable register bit 2 is set.

4. 5 volt undervoltage is detected and interrupt enable register bit 3 is set.

5. +12 under/over voltage is detected and interrupt enable register bit 4 is set.

6. -12 under/over voltage is detected and interrupt enable register bit 5 is set.

7. The fan control circuit hits maximum or zero power and interrupt enable register bit 6 is set.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 25 26

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